Q. 34 A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two dimensional array of size 512#512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2, P1 :
P1:
for (i=; i<512; i++) { for (j=; j<512; j++) { x +=A[i] [j]; } }
P2:
for (i=; i<512; i++) { for (j=; j<512; j++) { x +=A[j] [i]; } }
P1P1 and P2P2 are executed independently with the same initial state, namely, the array AA is not in the cache and ii, jj, xx are in registers. Let the number of cache misses experienced by P1P1 be M1M1and that for P2P2 be M2M2.
The value of M1M1 is:
(A)
(B)20482048
(C)1638416384
(D)262144
Answer: (C)
Explanation:
