Q. 48 Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average
cycles per instruction of four. The same processor is upgraded to a pipelined
processor with five stages; but due to the internal pipeline delay, the clock speed
is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The
speed up achieved in this pipelined processor is ______.
(A) 3.2
(B) 3.0
(C) 2.2
(D) 2.0
Answer: (A)
Explanation:
