Gate CS-2019 Question Paper With Solutions

Q. 54 A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60 MHz clock. To service a cache-miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle.

The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is _________ × 106 bytes/sec.

Note: This was Numerical Type question.

(A) 160

(B) 128

(C) 256

(D) 320

Answer: (A)


Gate CS-2019 Question Paper With Solutions

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