Gate EC-2003 Question Paper With Solutions

Q. 55 A 4 bit ripple counter and a bit synchronous counter are made using flip flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

(A) R = 10 ns, S = 40 ns

(B) R = 40 ns, S = 10 ns

(C) R = 10 ns S = 30 ns

(D) R = 30 ns, S = 10 ns

Answer: (B) 

Explanation:

Gate EC-2003 Question Paper With Solutions

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