Q. 45 Consider an instruction pipeline with five stages without any branch prediction:
Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute
Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI
and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate
storage buffers after each stage and the delay of each buffer is 1 ns. A program
consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor.
Instruction I4 is the only branch instruction and its branch target is I9. If the
branch is taken during the execution of this program, the time (in ns) needed to
complete the program is
(A) 132
(B) 165
(C) 176
(D) 328
Answer: (B)
Explanation:
