Q. 14 A-5 stage pipelined processor has Instruction Fetch. (IF), Instruction Decode
(ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO)
stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction.
The PO stage takes 1 clock cycle for ADD and SUB instruction. The PO stage
takes 1 stake clock cycle for ADD and SUB instructions 3 clock cycles for
MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand
forwarding is used in the pipeline. What is the number of clock cycles needed to
execute the following sequence of instructions ?
(A) 13
(B) 15
(C) 17
(D) 19
Answer: (B)
Explanation:
